git: d3c1b26d2f - main - arch-handbook/usb: Fix typo for USB

The branch main has been updated by dbaio:

URL: https://cgit.FreeBSD.org/doc/commit/?id=d3c1b26d2fb352adb8e5ee74515ab38b99203d17

commit d3c1b26d2fb352adb8e5ee74515ab38b99203d17
Author:     Shi-Xin Huang <shixinh70@gapp.nthu.edu.tw>
AuthorDate: 2024-01-04 04:55:30 +0000
Commit:     Danilo G. Baio <dbaio@FreeBSD.org>
CommitDate: 2024-01-18 00:15:27 +0000

    arch-handbook/usb: Fix typo for USB
    
    There's a missing space between "that" and "frame".
    
    Event:  Advanced UNIX Programming Course (Fall’23) at NTHU
    Reviewed by:    lwhsu
    Pull Request:   https://github.com/freebsd/freebsd-doc/pull/322
---
 documentation/content/en/books/arch-handbook/usb/_index.adoc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/documentation/content/en/books/arch-handbook/usb/_index.adoc b/documentation/content/en/books/arch-handbook/usb/_index.adoc
index f88db60bc8..13631b52b2 100644
--- a/documentation/content/en/books/arch-handbook/usb/_index.adoc
+++ b/documentation/content/en/books/arch-handbook/usb/_index.adoc
@@ -93,7 +93,7 @@ The UHCI host controller maintains a framelist with 1024 pointers to per frame d
 
 Each transfer consists of one or more packets. The UHCI driver splits large transfers into multiple packets. For every transfer, apart from isochronous transfers, a QH is allocated. For every type of transfer these QHs are collected at a QH for that type. Isochronous transfers have to be executed first because of the fixed latency requirement and are directly referred to by the pointer in the framelist. The last isochronous TD refers to the QH for interrupt transfers for that frame. All QHs for interrupt transfers point at the QH for control transfers, which in turn points at the QH for bulk transfers. The following diagram gives a graphical overview of this:
 
-This results in the following schedule being run in each frame. After fetching the pointer for the current frame from the framelist the controller first executes the TDs for all the isochronous packets in that frame. The last of these TDs refers to the QH for the interrupt transfers for thatframe. The host controller will then descend from that QH to the QHs for the individual interrupt transfers. After finishing that queue, the QH for the interrupt transfers will refer the controller to the QH for all control transfers. It will execute all the subqueues scheduled there, followed by all the transfers queued at the bulk QH. To facilitate the handling of finished or failed transfers different types of interrupts are generated by the hardware at the end of each frame. In the last TD for a transfer the Interrupt-On Completion bit is set by the HC driver to flag an interrupt when the transfer has completed. An error interrupt is flagged if a TD reaches its maximum error count. If the sho
 rt packet detect bit is set in a TD and less than the set packet length is transferred this interrupt is flagged to notify the controller driver of the completed transfer. It is the host controller driver's task to find out which transfer has completed or produced an error. When called the interrupt service routine will locate all the finished transfers and call their callbacks.
+This results in the following schedule being run in each frame. After fetching the pointer for the current frame from the framelist the controller first executes the TDs for all the isochronous packets in that frame. The last of these TDs refers to the QH for the interrupt transfers for that frame. The host controller will then descend from that QH to the QHs for the individual interrupt transfers. After finishing that queue, the QH for the interrupt transfers will refer the controller to the QH for all control transfers. It will execute all the subqueues scheduled there, followed by all the transfers queued at the bulk QH. To facilitate the handling of finished or failed transfers different types of interrupts are generated by the hardware at the end of each frame. In the last TD for a transfer the Interrupt-On Completion bit is set by the HC driver to flag an interrupt when the transfer has completed. An error interrupt is flagged if a TD reaches its maximum error count. If the sh
 ort packet detect bit is set in a TD and less than the set packet length is transferred this interrupt is flagged to notify the controller driver of the completed transfer. It is the host controller driver's task to find out which transfer has completed or produced an error. When called the interrupt service routine will locate all the finished transfers and call their callbacks.
 
 Refer to the UHCI Specification for a more elaborate description.