git: 53e1af5a1094 - main - arm64: Decode the ID_AA64PFR2_EL1 register

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=53e1af5a1094ec37412bc33b739de72ed723c428

commit 53e1af5a1094ec37412bc33b739de72ed723c428
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2023-07-06 14:48:42 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2023-07-28 11:53:02 +0000

    arm64: Decode the ID_AA64PFR2_EL1 register
    
    No fields have been defined, but it has been documented in the
    Architecture Reference Manual.
    
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D40897
---
 sys/arm64/arm64/identcpu.c | 14 ++++++++++++++
 sys/arm64/include/armreg.h |  8 ++++++++
 2 files changed, 22 insertions(+)

diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
index 578c2b629397..2347d27c69e1 100644
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -143,6 +143,7 @@ struct cpu_desc {
 	uint64_t	id_aa64mmfr4;
 	uint64_t	id_aa64pfr0;
 	uint64_t	id_aa64pfr1;
+	uint64_t	id_aa64pfr2;
 	uint64_t	id_aa64zfr0;
 	uint64_t	ctr;
 #ifdef COMPAT_FREEBSD32
@@ -1542,6 +1543,12 @@ static const struct mrs_field id_aa64pfr1_fields[] = {
 };
 
 
+/* ID_AA64PFR2_EL1 */
+static const struct mrs_field id_aa64pfr2_fields[] = {
+	MRS_FIELD_END,
+};
+
+
 /* ID_AA64ZFR0_EL1 */
 static const struct mrs_field_value id_aa64zfr0_f64mm[] = {
 	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F64MM, NONE, IMPL),
@@ -1844,6 +1851,7 @@ static const struct mrs_user_reg user_regs[] = {
 
 	USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0),
 	USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1),
+	USER_REG(ID_AA64PFR2_EL1, id_aa64pfr2),
 
 	USER_REG(ID_AA64ZFR0_EL1, id_aa64zfr0),
 
@@ -2552,6 +2560,11 @@ print_cpu_features(u_int cpu, struct cpu_desc *desc,
 		print_id_register(sb, "Processor Features 1",
 		    desc->id_aa64pfr1, id_aa64pfr1_fields);
 
+	/* AArch64 Processor Feature Register 2 */
+	if (SHOULD_PRINT_REG(id_aa64pfr2))
+		print_id_register(sb, "Processor Features 2",
+		    desc->id_aa64pfr2, id_aa64pfr2_fields);
+
 	/* AArch64 Memory Model Feature Register 0 */
 	if (SHOULD_PRINT_REG(id_aa64mmfr0))
 		print_id_register(sb, "Memory Model Features 0",
@@ -2695,6 +2708,7 @@ identify_cpu(u_int cpu)
 	desc->id_aa64mmfr4 = READ_SPECIALREG(id_aa64mmfr4_el1);
 	desc->id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
 	desc->id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
+	desc->id_aa64pfr2 = READ_SPECIALREG(id_aa64pfr2_el1);
 
 	/*
 	 * ID_AA64ZFR0_EL1 is only valid when at least one of:
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 7624adf9eee4..92a62c8d2b53 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1258,6 +1258,14 @@
 #define	 ID_AA64PFR1_NMI_NONE		(UL(0x0) << ID_AA64PFR1_NMI_SHIFT)
 #define	 ID_AA64PFR1_NMI_IMPL		(UL(0x1) << ID_AA64PFR1_NMI_SHIFT)
 
+/* ID_AA64PFR2_EL1 */
+#define	ID_AA64PFR2_EL1			MRS_REG(ID_AA64PFR2_EL1)
+#define	ID_AA64PFR2_EL1_op0		3
+#define	ID_AA64PFR2_EL1_op1		0
+#define	ID_AA64PFR2_EL1_CRn		0
+#define	ID_AA64PFR2_EL1_CRm		4
+#define	ID_AA64PFR2_EL1_op2		2
+
 /* ID_AA64ZFR0_EL1 */
 #define	ID_AA64ZFR0_EL1			MRS_REG(ID_AA64ZFR0_EL1)
 #define	ID_AA64ZFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1)